Digital differential analyzers



Nov. 7, 1961 R. M. BECK ETAL DIGITAL DIFFERENTIAL ANALYZERS @Q wk led Feb. l5

ANov. 7, 1961 R. M. BECK ETAL DIGITAL DIFFERENTIAL ANALYzERs Armin/5y Nov. 7, 1961 R. M. BECK ETAL DIGITAL DIFFERENTIAL ANALYzERs NRM.

INVENTORS iam-ern 5564/ 13 Sheets-Sheet 5 .NNI

NNN

NSM

Wim

Filed Feb. 15, 1954 Nov. 7, 1961 R. M. BECK ErAL 3,007,641

DIGITAL DIFFERENTIAL ANALYZERS I /47'TOR'NE V Nov. 7, 1961 R. M. BECK Erm.

DIGITAL DIFFERENTIAL ANALYzFRs Filed Feb. 15. 1954 www HSS@

NGN

Nov.l 7, 1961 R. M. BECK r-:rAL

DIGITAL DIFFERENTIAL ANALYzExs 13 Sheets-Sheet 6 Filed Feb. l5, 1954 Nov. 7, 1961 R. M. BECK ETAL DIGITAL DIFFERENTIAL ANALYzERs RSMNYM mkv@ .NSMYG Nb@ Filed Feb. 15, 1954 Nov. 7, 1961 R. M. BECK ETAL DIGITAL DIFFERENTIAL ANALYzERs 15 Sheets-Sheet 8 Filed Feb. 15. 1954 5 wm ma@ I? V .fn ma x mmh www@ i Sw Y M B @JMJ FQ Si QQ W \m\ S@ n R ,Smn A v W Wl E QQ* Nov. 7, 1961 BECK Erm. 3,007,641

DIGITAL DIFFERENTIAL ANALYZERS Filed Feb. 15, 1954 13 Sheets-Sheet 9 l 'Mllllll /4 /az f6 /5 CHAN/VEL CHAN/VEL i HAN/va /64 22 lll I Ul Eli I /M/V/VEL Z4 INVENTORS ,waiver/z 35:4/ Gioia: M ,aww/a wwe-mk Nov. 7, 1961 Filed Feb. 15. 1954 R. M. BECK ETAL DIGITAL DIFFERENTIAL ANALYZERS 13 Sheets-Sheet 10 ,Y Tan ,Y

EJE

'MQW

Nov. 7, 1961 R. M. BECK :TAL 3,007,641

DIGITAL DIFFERENTIAL ANALYZERS Filed Feb. 15, 1954 13 Sheets-Sheet 11 1N VEN TORS maier/v for Nov. 7, 1961 R. M. BECK ETAL 3,007,641

DIGITAL DIFFERNTIAL ANALYZERS Filed Feb. 15, 1954 15 Sheets-Sheet 12 4 3 z VM@ 4 5 2 Van o o o o +4 o +5 o o o +5 o o +7 0 +7 o 0 o +5 0 a +5 0 0 +2 0 o 0 +2 0 a o 0 0 0 l H 0 o o 0 0 0 0 0 a o o 0 o o a 5 0 .5

0 e o o- -6 0 0 -a 0 o a -s 14 EJE I I I i 44 A5 AZ A/T--vwf INVENTORS v mmm Unite States Patent @Hice 3,007,641 Patented Nov. 7, 1961 3,007,641 DIGITAL DIFFERENTIAL ANALYZERS Robert M. Beck and George W. Fairchild, Inglewood,

Vernon P. Magnuson, Gardena, and Max Palevsky, Los

Angeles, Calif., assignors to The Bendix Corporation,

a corporation of Delaware Filed Feb. 15, 1954, Ser. No. 410,231 4 Claims. (Cl. 23S-152) This invention relates to digital differential analyzers and more particularly to an analyzer for utilizing decimal digits to enhance its ease of operation and for facilitating scaling in the decimal system.

-In co-pending application Serial No. 217,478, led March 26, 1951, now Patent No. 2,900,134, by Floyd G. Steele and William S. Collison, a digital diiferential analyzer is disclosed for solving complex differential problems by digital steps. The analyzer has the advantages of both digital computers and differential analyzers. The analyzer obtains the advantage of diierential analyzers in that it is relatively small in construction. The analyzer also -has the advantage of digital computers in its speed and accuracy of operation. By combining these advantages, a computer is obtained which is able to solve cornplex differential equations even though it is housed in a cabinet smaller than Ia desk.

The digital differential analyzers now in use operate in the binary system to obtain the solution of digital problems. These systems have been entirely satisfactory from the standpoint of operation. However, operators of the machine have expressed some desire for an analyzer which will operate on a decimal basis. It has been the opinion of these people that a machine operating on a decimal basis can be initially coded relatively easily and that the results obtained vduring and after the solution of a problem can also be read and digested easily.

One of the difficulties in converting from a binary system to a decimal system results from problems of scaling. In the binary `system the scale progresses in the relationship l, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, etc., for successive digit positions. In the decimal system, the scale progresses in the relationship 1, 10, 100, 1,000, etc., for successive digit positions. As can be seen, the scale values in the decimal system are spaced further apart numerically than the scale values in the binary system. This spread of scale values in the decimal system may restrict the full utilization of the digital differential analyzer under certain conditions.

This invention provides a digital diierential analyzer for converting binary information into decimal information and for solving differential problems on the basis of the decimal information. The analyzer also includes members for providing a multiplication by such integers as 2 or 5. The analyzer provides such multiplications by the inclusion of a relatively few components in addition lto these required to produce the decimal operation. By providing a multiplication by such integers as 2 or 5, the scale in the decimal system is able to progress in the relationship 1, 2, 5, l0, 20, 50, 100, 200, 500, 1,000, etc. In -this Way, the scale values are able to approach the scale values in the binary system in closeness of numerical spacing.

An object of this invention is to provide a digital differential analyzer which operates -in digital steps to obtain a solution of complex dilerential problems.

Another object -is to provide an analyzer of the above character which is capable of being coded and of operating on a decimal basis to solve differential problems.

A further object is to provide an analyzer of the above character for multiplying any particular decimal value by such lintegers as 2 or 5 to increase the scale values of 2 a decimal machine so that it approaches the' scale values of a binary machine.

Still another object is -to provide an anlyzer of the above character in which only a relatively few components are required to be included in an analyzer operating on a decimal basis to provide multiplications of any output value by such integers as 2 or 5.

A still further object is to provide a method of solving differential problems in digital steps and on a decimal basis and of multiplying the output values by such integers as 2 or 5.

Other objects and advantages will be apparent from a detailed description of the information and from the appended drawings and claims.

In the drawings:

FIGURE 1 .is a simplified block diagram which schematically illustrates a digital differential analyzer forming one embodiment of this invention;

FIGURES 2, 3, 4, 5, 6, and 7 are schematic diagrams, partly in block form and partly in perspective, illustrating in some detail the `digital differential analyzer in FIG- URE 1;

FIGURE 8 is a circuit diagram of a flip-dop unit which forms a basic stage of the analyzer shown in FIGURE 1 and of the analyzer shown in `FIGURES 2 to 7, inclusive;

FIGURE 9 is a block diagram illustrating the operation of one of the integrators forming part of the digital differential analyzer shown in FIGURE 1 and in FIG- URES 2 to 7, inclusive;

FIGURE 10 is a curve illustrating the operation of an integrator such as the integrator shown in FIGURE 9;

FIGURE 11 is a chart which illustrates how dilerent par-ts of an integrator such as that shown in FIGURE 9 are coded lto control the operation of the integrator;

FIGURE 12 is a schematic diagram illustrating the relationship between different integrators forming the digital differential analyzer shown in FIGURE 1 and in FIG- URES 2 to 7, inclusive, when the analyzer is solving a particular problem;

FIGURE 13 is a chart illustrating the operation of certain of the components forming part of the analyzer shown in FIGURE l and in FIGURES 2 to 7, inclusive;

FIGURE 14 is a chart which illustrates the operation of certain of the components shown in FIGURES 2 to 7, inclusive;

FIGURE 15 is a chart illustrating the operation of certain of the components in analyzers now in use to provide a comparison with the chart shown in FIGURE 14; and

FIGURES 16, 17, and 18 are charts which illustrate the operation of various components shown in FIGURES 2 to 7, inclusive.

A simplilied block diagram is sho-wn in FIGURE 1 of an analyzer for solving differential problems by digital steps. The analyzer includes a drum 10 (schematically shown in FIGURES 2 to 7, inclusive) adapted to be rotated by a suitable motor (not shown). A thin coating 12 (FIGURE 2) of magnetic material is applied to the periphery of the drum. The coating 12 can be considered as being ldivided into a plurality of annular channels 14, 16, 18, 20, 22, 24 and 26. These channels are shown schematically in FIGURE l in separated relationship for purposes of convenience. Each of the channels is separated by by a sufficient distance from its adjacent channel so as to be substantially unaffected by the magnetic information provided in the adjacent channel.

The circumferential distance of each channel may be considered as being divided into a plurality of positions. Each of the positions is suiciently separated from its adjacent positions to receive a different magnetization than that provided on the adjacent positions. For example, approximately 1160 equally spaced pulse positions may be provided in each channel when the drum has a radius of approximately four inches.

A plurality of toroidal coils are positioned adjacent to each of the channels 14, 16, 18, 20, 22, 24 and 26. For example, coils 27, 28 and 30 a-re provided in contiguous relationship to the channel 14. These coils are shown schematically in FIGURE 1. Similarly, coils 32, 34 and 36; coils 38, 40 and 42; coils 44, 46 and 48; coils 50, 52 and 54; and coils 56, 58 and 60 are associated with the channels 16, 1'8, 20, 22 and 24, respectively. A single coil 62 is disposed adjacent the channel 26.

The coils 27 and 30 are effectively separated from each other by approximately 104 pulse positions, and the coil 28 is disposed at an intermediate position between the coils 27 and 30. The coil 30 is adapted to provide signals in a pattern dependent on the operation of the digital differential analyzer and to induce the corresponding magnetic pattern on the drum 10 as the drum rotates. The pattern induced on the drum 10 by the coil 30 is of the binary form in which a magnetization in one circumferential direction indicates one value and a magnetization in the other direction indicates a second value.

The coil 27 is adapted to pick up the changes in the direction of magnetization in `the channel 14 as the drum rotates. The coil 28 is adapted to produce a substantially constant signal for returning the direction of magnetization on the drum to that representing a value of after the magnetic pattern on the drum has been converted into a corresponding electrical pattern by the coil 27.

The coils 32, 34 and 36 are separated from one another by distances corresponding to the distances between the coils 27, 28 and 30 and are adapted to perform functions similar to those performed by the coils 27, 28 and 30, respectively. The coils 38, 40 and 42 and the coils 44, 46 and 48 are also separated in the channels 18 and 20 in a similar manner to the separation of the coils in the channel 14 and are adapted to perform functions corresponding to those performed by the coils 27, 28 and 30, respectively.

The coils 52 and 58 are adapted to operate in a manner similar to the coil 30 to provide a magnetic pattern in the channels 22 and 24, respectively, in a pattern dependent upon the problem to be solved. The coils 52 and S8 are effectively separated from the coils 54 and 60, respectively, by approximately 49 pulse positions during the operation of the analyzer to obtain the solution of a mathematical problem.

The coils 54 and 60 are adapted to produce signals in accordance with the magnetic pattern provided in their respective channels by the coils 52 and 58. The coils 50 Iand 56 are adapted to operate in a manner similar to the coil 28 to produce a zero direction of magnetization in the channels 22 and 24, respectively, after the patterns provided by the coils 52 and S8 have been utilized by the coils 54 and 60, respectively.

The coil 62 is adapted to produce a cycle of a signal approximating a sine wave as each pulse position in the channel 26 moves past the coil. The coil 62 produces sinusoidal signals because of the magnetic pattern permanently provided in the channel 26. This pattern remains constant regardless of the problem to be solved.

A counter 66 is connected to the coil 62 to count the cycles of the sine waves in the channel 26 as the drum rotates. The counter 66 is formed from a plurality of multivibrators connected in cascade arrangement and is adapted to count successive sine signals in a numerical range from "1 to 48. Upon each count of 48, the counter 66 is adapted to return to its initial state for the commencement of a new count. As will be disclosed in detail hereinafter, a new integrator is presented for computation upon the completion of each count of 48.

Similarly, a counter 67 is formed from a plurality of multivibrators in cascade arrangement. The counter 67v is connected to the counter 66 to count the number of times that a full count is obtained in the counter 66. For example, the counter 67 may count up to 22 full counts in the counter 66 before returning to its initial state for the initiation of a new count. In this Way, the counters 66 and 67 divide the drum 10 into 22 integrator sections each having 48 pulse positions.

As schematically shown in FIGURE 1, the output signals induced in the coil 32 are introduced to` a gate circuit 68, which also has signals applied to it through a line 70 from the counter 66. 'Ihe output signals from the gate circuit 68 are in turn applied through an or network 72 to the coil 36. Similarly, a gate circuit 74 receives signals from the coil 38 and through the line 70 from the counter 66. The output terminal of the gate circuit 74 is connected to an input terminal of an or netwo-rk 76 having its output terminal connected to the coil 42.

The coil 32 is not only connected to the gate circuit 68 but also to an input terminal of a gate circuit 78 having other input terminals connected to the coils 54 and 60 and through the line 70 to the counter 66. The output from the gate circuit 78 passes to a counter 80 formed from a plurality of multivibrators in cascade arrangement. The output from the counter 80 is in turn applied to input terminals of a plurality of gate circuits which are designated in FIGURE l by a single block at y82 and which have other input terminals connected to the plate of the left tube in a multivibrator 90. The output terminals of the gate circuits 82 are connected to input terminals of an adder 92.

'I'he signals from the coil 32 are also introduced to an input terminal of a gate circuit 94 having another input terminal connected through a line 96 to the counter 66. The output from the gate circuit 94 is applied to the grid of the left tube in a bistable multivibrator 98, the grid of the right tube in the multivibrator being connected through `a line 100 to the counter 66. The plate of the left tube in the multivibrator 98 -is connected to an input terminal of a gate circuit 104, another input terminal of which is connected to the coil 62. The signals passing through the gate circuit 104 are introduced directly to the grid of the left tube in the multivibrator and through an or network 106 to the grid of the right tube in the multivibrator, Signals also pass from the counter 66 through the line 100 and the or network 106 to the grid of the right tube in the multivibrator 90.

In addition to receiving the signals from the gate circuit 82, the adder 92 also receives signals from the coils 27, 32, 38 and 44. The signals from the gate circuits 82 are arithmetically combined in the adder 92 with the signals from the coils 27, 32, 38 and 44. The results obtained are applied through an or network 108 to the coil 30, through the or network 72 to the coil 36, through the or network 76 to the coil 42, and through an or network 109 to the coil 48.

The pulses induced in the coils 27, 32, 38 and 44 are also applied to input terminals of gate circuits designated in FIGURE l by a single block at 110. Connections are also made to input terminals of the gate circuit 110 from the plate of the left tube in the multivibrator 90 and from the plate of the left tube in a multivibrator 112. Connections are respectively made to the grids of the left and right tubes in the multivibrator 112 .from a gate circuit 114 and through the line from the counter 66. The gate circuit 114 in turn receives signals from the coils 38 and 54 and through the line 70 from the counter 66.

The output signals from the gate circuits are introduced to the adder 92 through suitable delay lines, designated in FIGURE l at 116, for combination with the signals from the coils 27, 32, 38 and 44. The delay lines 116 may be bistable multivibrators to` delay by one pulse position the information from the gate circuits 110. The output signals obtained by the adder 92 are applied to the coils 30, 36, 42 and 48 through the or networks 108, 72, 76 and 109, respectively.

The output signals passing from the adder 92 to the coil 48 are also applied to gate circuits 120 and 122, each of which has an input terminal connected through the line 100 to the counter 66. The output signals from the gate circuits 120 and 122 respectively pass through or networks 124 and 126 for introduction to the coils 52 and 58. The or networks 124 and 126 also respectively receive signals from gate circuits 128 and 130. Connections are made to input terminals of the gate circuit 128 from the coil 54 and through a line 132 from the counter 66. Similarly, input terminals of the gate circuit 130 are connected to the coil 60 and line 132.

The coil 27 is connected directly to an input terminal of a gate circuit 13'4 having another input terminal connected through the line 100 to the counter 66. The output from the gate circuit 134 is introduced to the or network 108 and is also introduced to a gate circuit 136 to control the operation of the gate circuit 136 in assimilating information introduced to the gate circuit 136 from various output terminals of the adder 92. The output from the gate circuit 136 through the or network 124 is introduced to the coil 52.

Similarly, a gate circuit 13S :receives a voltage from the line 100 and from the coil 44. The output from the gate circuit 138 passes to the or network 109 for recordation by the coil 48 in the channel 20. The output from the ygate circuit 138 also controls the operation of a gate circuit 139 in assimilating information introduced to the gate circuit 139 from various output terminals of the adder 92. A connection is made from the output terminal of the gate circuit 139 to an input terminal of the or network 124.

'Ihe digital differential analyzer as illustnatively described above in simplified form is adapted to provide the solution of differential equations. For example, it may provide the solution of the problem of evaluating the integral of a general equation y=f(x) so as to obtain a function fydx= ff(x)dx, where ](x) represents a function of x and ff(x)dx represents the integral of the function. If a curve y=f(x) is plotted with x as the abscissa and y as the ordinate the analyzer obtains the relationship fydx=ff(x)dx by computing the area under the curve y=f(x). By determining the area under the curve y==f(x), the analyzer performs electronically operations that may sometimes be performed mentally by a skilled mathematician when the problem to be solved is relatively simple.

The analyzer obtains the value of the function fydx=ff(x)dx by producing small increments of x. These increments may be represented by the symbol Ax. For each Ax increment, the analyzer determines the value of y and obtains the product yAx. This product yAx approximates the area under the curve y=f(x) yfor each Ax increment, as indicated in FIG- URE lO by the shaded area 140 for a particular Ax increment. If the product yAx is obtained for successive Ax increments and if all of the yAx increments are added together, the area under the interval of the curve representing f(x) from x to x may be approxim-ated. A rela-tively yaccurate approximation may be obtained by decreasing the value of each Ax increment.

An integrator for determining the yAx increments and for storing the cumulative values of these increments is shown in FIGURE 9. 'Iihe integrator includes `a transfer stage 142 for obtaining Ax increments at periodic intervals through a line 144. The integrator also has an integrand accumulator 146 for storing the value of the dependent quantity y and for receiving Ay increments through a line 148 from its own and from other integrators so as to vary the value of y in accordance with the function y=f(x). An output accumulator 150 is provided to receive yAx increments, to combine each yAx increment with the previous increments and to -deliver the cumulative value obtained to another integral accumulator or transfer stage while holding the remainder in store. A detailed explanation of this will be given hereafter.

The interrelationship between different integrators is illustrated in FIGURE l2 for a particular problem. This problem starts with a differential equation represented by As is mathematically known, the differential solution of this problem indicates that y=tan x. The interrelationship illustrated in FIGURE l2 utilizes this solution to generate the function tan x which is accumulated in the register of an output integrator. The integrators involved in the generation of the function tan x are i-ndicated in FIGURE 12 by blocks 152, 154, 156, 158 and 160. In Ieach integrator, the introduction of the Ax increments constituting changes in the independent variable quantity for the integrator is indicated by a line extending into the upper right position in the block. The Ay increments are introduced into the integrator through a line or a plurality of lines extending into the lower right portion of the block representing the integrator. The output of lthe integrator is obtained from a line extending from an intermediate position at the right side of the appropriate block.

As will be seen in FIGURE 12, Ax increments of the independent variable for a particular integrator may be obtained from the output of another integrator. For example, in FIGURE l2, the Ax increments for the integrators 154 and 156 are obtained from the output of the integrator 152. Similarly, Ay increments for a particular integrator may be obtained from the output of other integrators as well as from the output of the integrator itself. For example, Ay increments for the integrators 154 and 158 are obtained from the output of the integrator 152.

The Ay and Ax increments for each integrator are actually `determined from a coded pattern provided in the channels 16 and 18, respectively. As previously disclosed, the pulse positions in each channel are subdivided into 22 integrator sections each having 4S pulse positions. The first 22 positions in each integrator section in the channel 18 are coded to indicate a Ax increment. Since the first 22 positions in the channel 18` for each integrator section correspond in number to the 22 integrators in the analyzer, each integrator can receive a Ax increment from the output of any of the other integrators. This can be effectuated by providing a pulse in the channel 18 in a particular one `of the rst 22 positions for the integrator.

lFor example, the Ax increments for the integrator 154 in FIGURE 12 would be coded in a particular one of the 22 positions in the channel 18. As will be disclosed in detail hereinafter, the particular position corresponds to the time at which the output from the integrato-r 152 appears on the coils 54 and 60. In FIGURE l1, a pulse 162 is shown as being recorded in the channel 18 in the 11th pulse position for a particular integrator section.

A pulse in the channel 18 in one of the first 22 positions for a particular integrator section indicates that a Ax increment may be made for the integrator. However, such a pulse does not indicate whether an increment will actually be made and, if so, whether the polarity of such increment will be positive or negative. The actual occurrence of a Ax increment for the integrator is indicated by the presence or absence of a coincidental pulse in the channel 22. If a positive pulse is picked up from the channel 22 by the coil 54 at the same time as the pulse representing a possible Ax increment for a particular integrator is picked up by the coil 38, a Ax increment for the integrator actually occurs. For example, the pulse 162 in FIGURE ll indicates` an actual Ax increment for a particular integrator since it coincides in time with a pulse 164 in the channel 22. A Ax increment is not obtained for the integrator if a pulse does not appear in the channel 22 at the same time as the pulse in the channel 18.

The polarity of each Ax increment is determined by the presence or absence of a coincidental pulse in the channel 24. If a pulse is picked up from the channel 24 by the coil 60 at the same time that pulses indicating an actual Ax increment for a particular integrator are picked up the coils 38 and 54, the Ax increment for the integrator is positive. The Ax increment is negative if a pulse does not appear in the channel 24 at the same time as the pulses in the channels 18 and 22. For example, the pulse 162 in FIGURE 11 indicates a negative Ax increment since a pulse does not appear in the channel 24 simultaneously with the occurrence of the pulses 162 and 164 in the channels 18 and 22, respectively.

The first 22 positions in the channel 16 for each integrator are coded to indicate Ay increments in a manner similar to the coding of corresponding positions in the channel 18 to indicated Ax increments. Since the first 22 positions in each integrator section correspond to the 22 integrators in the digital differential analyzer, each integrator section is coded in particular ones of the first 22 positions in the channel 16 so as to receive the outputs from certain integrators in accordance with the problem to be solved. For example, a pulse would be coded in the channel 16 in a particular one of the first 22 positions for the integrator 158 in FIGURE 12 so as to coincide With the time at which the output from the integrator 152 is made available to the coils 54 and 60 in the channels 22 and 24, respectively. Although only one Ax increment can be obtained for an integrator upon each revolution of the drum, several Ay increments can be obtained. This may be seen by the pulses 168 and 170 in the channel 16 in FIGURE 11.

Each pulse in the first 22 positions in the channel 16 for each integrator represents the possibility of a Ay increment but does not indicate the actual occurrence of such an increment or the polarity of the increment. The actual occurrence of the increment is indicated by the presence or absence of a pulse in the channel 22 at the same time that the pulse in the channel 16 is made available to the coil 32. For example, the pulse 168 in FIGURE 11 indicates an actual Ay increment for a particular integrator since it coincides in time with a pulse 172 in the channel 22. However, no Ay increment is obtained when the pulse 170 is picked up by the coil 32 since there is no coincidental pulse in the channel 22.

The sign of each actual Ay increment is indicated by the presence or absence of a pulse in the channel 24 at the time that pulses in the channels 16 and 22 are simultaneously made available to the coils 32 and 54. For example, the pulse 168 in FIGURE 11 indicates a positive Ay increment for a particular integrator since a pulse 174 appears in the channel 24 at the time that the pulses 168 and 172 are picked up by the coils 32 and 54, respectively.

Since the interrelationship between the different integrators remains constant during the solution of a particular porblem, the coding pulses in the channels 16 and 18 for the first 22 positions of the integrator section must be retained during the computation. Retention of the pulses in the channel 16 is effectuated by the gate circuit 68, which remains open during the first 22 positions in each integrator to pass the coded information in these positions. The gate circuit 68 opens during these pulse positions because of the introduction of a relatively high voltage through the line 70 from the counter 66. The signals then pass through the or network 72 for recordation by the coil 36 in the channel 16. Similarly, the gate circuit 74 opens during the first 22 positions for each integrator section so that the coding informa- 8 tion can pass through the or network 76 for recordation by the coil 42 in the channel 18.

It should be appreciated that the gate circuits similar to the circuit 68 operate tto pass information only when positive pulses are simultaneously introduced to all of the input terminals of the circuit. In computer terminology such circuits have been designated as and networks. The term or networks is also common in computer terminology. Such circuits operate to pass such information when any one of their input terminals receives a relatively high voltage. Such or networks are shown in the drawings as triangles and are exemplified by the networks '72 and 76.

During the rst 22 positions of each integrator section the gate circuit 78 operates to determine the occurrence of Ay increments for the integrator and the polarity of each such increment. The gate circuit 78 makes such determinations by comparing the pulses from the coil 32 with the pulses from the coils 54 and 60. Each pulse induced in `the coil 32 in the first 22 positions of an integrator section indicates that a Ay increment can be obtained. As previously disclosed, the particular position in which a pulse occurs determines for an integrator which of the other integrators in the analyzer provides Ay increments for lthe integrator. The simultaneous production of a pulse by the coil 54 indicates that a Ay increment has actually occurred. When the coil 60 also produces a simultaneous pulse, the gate circuit 78 indicates that the Ay increment has a positive polarity.

At the same time that the gate circuit 78 operates to determine the occurrence of Ay increments for an integrator and the polarity of each such increment, the counter 80 arithmetically combines each such Ay increment. For example, a signal passing to the counter 80 from the gate circuit 78 may cause the circuit to provide a numerical indication of +4 when an indication of +3 was previously provided by the counter. Similarly, the indications in the counter 80 may change from a value of +3 to a value of 4 upon the introduction of a negative signal from the gate circuit 78.

The counter 80 retains in binary form the numerical information relating to the cumulative value of the Ay increments for an integrator. The counter 80 retains the information in binary form since it comprises a plurality of multivibrators arranged in cascade relationship. In this embodiment, four multivibrators in cascade arrangement are provided. For example, with a resultant count of +5 for the Ay increments for a particular integrator, the first and third multivibrators in the cascade arrangef ment may be operated to indicate a binary pattern of 0101, where the least significant digit is at the right. In binary form, a pattern of 0101 indicates that Similarly, a value of +3 is indicated by a pattern of 0011, where the least significant digit is at the right.

As previously disclosed, the information controlling increments in the dependent quantity for each integrator is provided in the channel 16 in the first 22 pulse positions for each integrator. The information relating to the dependent quantity y itself occurs in the channels 14, 16, 18 and 20 after the 22nd pulse position for each integrator. As will be disclosed in detail hereinafter, a group of pulse indications simultaneously appearing in the channels 14, 16, 18 and 20 provides an indicationv as to the value of a decimal digit.

The information relating to the dependent quantity y for each integrator is preceded by a pulse in the channel 16 to indicate that the information which follows relates to the dependent quantity y. For example, a pulse may occur in pulse position 28 for an integrator to indicate that the subsequent information in the channels 14, 16, 18 and 20 relates in part to the dependent quantity y for the integrator. This pulse has been designated in copending application Serial No. 217,478 as the start pulse.

The ist-art pulse in the channel 16 is introduced to the gate circuit 94, which also receives signals through the line 96 from the counter 66. Since a relatively high voltage appears on the line 96 only af-ter the 22nd pulse position for each integrator, the start pulse is the first pulse which is able to pass through the gate circuit 94. This pulse passes to the grid of the left tube in the multivibrator 98 and cuts off the tube. The resultant relatively high voltage on the plate of the left tube in the multivibrator 98 is introduced to the gate circuit 104.

Because of its connection to the coil 62, the gate circuit 104 passes each clock signal in the channel 26 after a relatively high voltage is introduced to it from the multivibrator 98. The signals from the gate circuit 104 are introduced directly Ito the g-rid of the left tube in the multivibrator 30 and through the or network 106 to lthe grid of the right tube in the multivibrator. The first signal from the gate circuit 104 causes the left tube in the multivibrator 90 to become cut off for reasons which will be disclosed in detail hereafter. Upon the passage of a second signal through the gate circui-t 104, the grid of the right tube in the multivibrator 90 becomes 4cut off and the left tube starts to conduct.

Similarly, the left tube in the multivibrator 90 becomes alternately cut off upon the introduction of odd signals from the gate circuit 104 and the right multivibrator tube becomes cut off upon the introduction of even signals. At the 48th pulse position for each integrator, a signal is introduced from the counter 66 through the line 100 and the or7 network 106 to the grid of the right tube of the multivibrator 90 so as to cut off the tube. In this way, the multivibrator 90 is prepared to have its left tube cut off upon the passage ot the rst signal through the gate circuit 104 for the next integrator.

As previously disclosed, the plate of the left tube in the multivibrator 9i) becomes cut off upon the passage of the first signal through the gate circuit 104. When the left tube in the multivibrator 98 becomes cut off, a relatively high vol-tage is introduced from the plate of the tube to the gate circuits 82 to open the gate circuits for the introduction of information from the counter 80. It has already been disclosed that the infomation introduced to the gate circuits from the counter 80 relates to increments in the dependent quality y for each integrator.

The information from the counter 80 passes through the gate circuits 82 to the Iadder 92 for combination with the signals induced in the coils 27, 32, 38 and 44, respectively. At `alternate pulse positions, the signals induced in the coils 27, 32, 38 and 44 relate to the dependent quantity y for the integrator undergoing computation. For example, when the start pulse for an integrator occurs at pulse position 27 for the integrator, pulse position 28 constitutes the first information pulse. Information relating to the value of the dependent quantity y for the integrator is accordingly provided in the channels 14, 16, 18 and 20 in pulse position 28 for the integrator and subsequently in alternate pulse positions such as pulse positions 30, 32, 34, etc.

The information relating to the dependent quantity y for each integrator is provided in the channels 14, 16, 18 and 20 on a decimal basis. For example, when the start pulse occurs in pulse position 27, the information in the channels 14, 16, 18, and 20 for pulse position 28 provides an indication of a decimal number between and 9, inclusive. Similarly, the information in the channels 14, 16, 18 and 20I for pulse position 30 provides an indication of the tens digit such as 10, 20, 30, etc. The exact manner in which the signals in the channels 14, 16, 18 and 20y provide such decimal information will be disclosed in detail hereafter.

Since the information in the channels 14, 16, 18 and 2.0 relate to decimal indications in a particular decimal code and since the signals passing through the gate circuits 82 relate to binary information, the signals passing through the gate circuits 82 are rst converted to a decimal 10 basis of the particular code before they are combined with the signals induced in the coils 27, 32, 38 and 44. The correction required to produce this conversion to a decimal base and the circuitry required for such conversion will be described in detail subsequently in connection with the detailed system shown in FIGURES 2 to 7 inclusive. The resultant signals produced by the adder 92 provide an indication in decimal form of the new value of the dependent quantity for the integrator undergoing computation. These signals are introduced to the coils 30, 36, 42 and 48 for recordation in the channels 14, 16, 18 and 20, respectively.

The pulses induced in the coils 27, 32, 3-8 and 44 are not only introduced to the adder 92 but also to gate circuits 110. Since the gate circuits 110 are also connected to the plate of the left tube in the multivibrator 90, the gate circuits become prepared for opening at alternate pulse positions after the start pulse. In these pulse positions, informa-tion relating to the dependent quantity y for each integrator is presented in the channels` r14, 16, 18 and 20.

The gate circuits 110 become opened for the passage of information to the adder 92 only when a relatively high voltage is introduced to them from the plate of left tube in the multivibrator 112. Such a high voltage is produced on the plate of the left tube in the multivibrator 1.12 when a signal passes to the grid of the tube from the gate circuit 114 and since the gate circuit is connected through the line 70' lto the counter 66, it becomes prepared for opening only during the rst 22 pulse positions of each integrator. During these pulse positions, a signal passes through the gate circuit 114 when pulses of relatively high voltage are simultaneously induced in the coils 38 and 54. The pulse of relatively high vol-tage induced in the coil 318 indicates the possibility of a Ax increment for an integrator undergoing computation. When a pulse simultaneously is induced in the coil 54, an indication is provided that a Ax increment has actually occurred for the integrator.

Since the signal passing through the gate circuit 114 provides an indication that a Ax increment has actually occurred for an integrator, the voltage on the plate of the left tube in the multivibrator 112 becomes relatively high only -upon the actual occurrence of such an increment. When the voltage on the plate of the left tube in the mulivibrator 112 becomes high, it remains high during the time that the remaining pulse positions in the integrator are presented for computation. At pulse position 48 for the integrator, a signal is introduced to the grid of the right tube in the multivibrator 11.2 through the line from the counter 66 so as to cut off the right tube in the multivibrator and make the left tube conductive. In this way, the left tube in the multivibrator 112 is prepared to become triggered into a state of non-conductivity upon the occurrence of a Ax increment for the next integrator.

Because of the connection between the plate of the left tube in the multivibrator :112 and the gate circuits 110, information is able to pass through the gate circuits only when a Ax increment has actually occurred for an integrator. A-s previously disclosed, this information relates to the new value of the dependent quantity y for the integrator.

The information in the channels 14, 16, 18 and 20 relating to the value of the dependent quantity y for an integrator is delayed by one pulse position and is then differentially combined in the adder 92 with the signals in the channels 14, 16, 18 and 20` relating to the cumulative value of the differential combination yAx for the integrator. The new information relating to the cumulative value of the differential combination for each integrator is recorded in alternate pulse positions in the channels 14, 16, 18 and 20.

Sometimes, as -the yAx increments for an integrator are added to the cumulative value of the differential combinafor the integrator, an over-How is obtained in the information stored in the channelsy `14, 16, 18 and 20'. When an overflow occurs in the cumulative value of the differential combination for an integrator, the indications representing the cumulative value return to an intermediate value so that they can build up again to a relatively high value. At the same time, an over-flow pulse is produced by the adder 92 at pulse position 48 for the integrator. This pulse passes through the gate circuit 120 since the gate circuit opens at the last pulse position for each integrator because of its connection through the line 100 to the counter 66. The pulse then passes through the or network 124 for recordation by the coil 52 in the channel 22.

For example, a first pulse of relatively high voltage may be provided in the channel 22 at the 48th position of integrator 1. This pulse indicates that an overflow has occurred in the cumulative yAx value stored in the channel 18 for the integrator but the pulse does `not indicate whether the overflow is positive or negative. The pulse is indicated at 180 in the chart shown at FIGURE 13.

In all of the vertical columns in the chart shown in FIGURE 13, except for the two at the extreme right, numbers between l and 22 are shown corresponding to the 22 integrators in the digital differential analyzer. In the two columns at the extreme right, numbers are shown prefaced by the letters I and P. The letter l followed by a number indicates the particular integrator section, coinciding to a particular integrator that is moving past the coil 52 at any instant. For example, I3 indicates that a pulse position in the third integrator section is moving past the coil 52 in the channel 22. Similarly, a designation such as P13 indicates that the 13th pulse position in the particular integrator section is moving past the coil 52.

After the pulse 180 is recorded by the coil 52 in the channel 22, it advances from the coil 52 towards the coil 54. During this time, the first 47 positions of integrator section 2 are passing under the coil 52. At the P4812 position-or, in other words, the last position of integrator section 2-an indication is recorded by the coil 5 2 in the channel 22, as indicated at 182 in FIGURE 13. This indication shows whether or not an overflow has occurred in the channel 20 in the cumulative value of the yAx increments for the integratorA At the P113 position, the indication 180 passes through the gate circuit 128 and the or network 124 to the coil 52. The pulse passes through the gate circuit 128 since the gate circuit opens in the first 47 pulse positions of each integrator. After passing through the gate circuit 128 and the or network 124, the pulse 180 is again recorded by the coil 52 in the channel 22, this time at the pulse position adjacent to the indication 182.

Similarly, indications are provided in adjacent pulse positions to show whether or not an over-flow has occurred in the cumulative yAx value for each of the other integrators in the analyzer. These indications are recirculated by the gate circuit 128, which remains open during the first 47 pulse positions of each integrator. At the 48th position for e-ach integrator, the gate circuit 128 closes and prevents any recirculation of old information for the integrator.

At the same time that the gate circuit 128 closes, the gate circuit 120 opens. When the gate circuit 120 opens, the overflow information for the integrator section moving past the coil 52 is recorded in the channel 22. In this way, old over-flow information for an integrator is replaced by new over-flow information for the integrator every time that the integrator is presented for computation.

After the indications have been provided in the channel 22 for the 48th pulse position of each integrator, integrator 1 is presented for computation a second time. As the drum rotates through the first 22 positions for the integrator section, the output indications for the 22 integrators move in sequence past the coil 54. This causes the output indications in the channel 22 to become available for determining whether or not a Ax increment and Ay increments are actually obtained for the integrator during the second computation. The determination of the occurrence of an actual Ax increment and of actual Ay increments is made by respectively comparing the coding pulses in the channels 16 and 18 with the overflow pulses in the channel 22. The operation of the digital differential analyzer to obtain such a determination has been disclosed previously.

Since the digital differential analyzer operates on a decimal basis, an overflow in the yAx increments would occur only for a value of l0 or a power thereof. For example, Ithe overflow in the cumulative value of the yAx increment for an integrator would occur only for values of l0, 100, 1000, 10,000, etc. In comparison, an yoverflow could occur for values of 2, 4, 8, 16, 32, 64, 128, etc. in a -digital differential analyzer operating on a binary basis, such as in the analyzer disclosed in co-pending application Serial No. 217,478. Since an overflow can occur in the decimal System for a considerable smaller number of values than in the binary system, a certain rigidity in the operation of the digital differential analyzer might result.

This invention provides components for multiplying the cumulative value of the yAx increments for an integrator by such integers as 2 or 5. As la result of such multiplication, an overflow can occur in the cumulative value in the yAx increments for an integrator for such values as 2, 5, 10, 20, 50, 100, 200, 500, 1000, etc. As will be seen, this causes the possibilites of overflow in the decimal system to approach that which can occur in Ia binary system. In this way, a digital differential analyzer is provided which has the advantage of operating in the decimal system without losing any flexibility which results from operation in the binary system.

Multiplication by either 2 or 5 in the cumulative value of the yAx increments for an integrator is controlled by the inclusion of a positive pulse at the 48th pulse position for the integrator. When multiplication by 2 is to be provided for an integrator a positive pulse is provided in the channel 14 at pulse position 48 for the integrator. Similarly, a positive pulse is provided in the channel 20 for an integrator when the cumulative value of the yAx increments for the integrator is to be multiplied by When a positive pulse occurs in the channel 14 at pulse position 48 for an integrator, it passes through the gate circuit l134 which opens at this pulse position because of its connection through the line to counter 66. The signal passing through the gate circuit 134 is introduced through the or network 108 to the coil 30 for recordation in the channel 14. In this way, the signal is recirculated in the channel 14 in pulse position 48 for the integrator so as to control the operation of the integrator every time that the integrator is presented for computation.

The signal passing through the gate circuit 134 is also introduced to the gate circuit 136 to control the operation of the circuit 136. The circuit 136 in turn passes a signal upon the introduction to it of particular information from the adder 92. The particular information which is required in order for the gate circuit 136 to open will be disclosed in full detail hereafter. Upon the opening of the gate circuit 136, a signal passes through the gate circuit and the or network 124 to the coil 52 for recordation by the coil in the channel 22. As previously disclosed, a signal is recorded in channel 22 to indicate that an overflow in the cumulative value of yAx increments has occurred for an integrator.

Because of the operation of the gate circuit 136, a pulse is introduced to the coil 52 for such values as 5, 50, 500, 50,000, etc. Since an overflow would ordinarily occur for the integrator for such values as 10, 100, 1,000, 10,000, etc. the gate circuit 136 in effect operates to multiply the cumulative value of the yAx increments by 2.

In like manner, the gate circuit 138 passes a signal when a pulse occurs in the channel 20 in pulse position 48 for an integrator. This pulse indicates that the cumulative value of the yAx increments is to be multiplied by 5. It is introduced through the or network 109 to the coil 48 'for recordation n the channel 20 so that it will be available to control the operation of the integrator every time that the integrator is presented for computation.

The output signal from rthe gate circuit 1x38 also contro-ls the operation of the gate circuit 139' so that the gate circuit 139 passes a signal `for values of 2, 20, 200, 2,000, etc. This signal passes through the or network 124 to the coil 52 for recordation in the channel 22 to provide an indication that an overilow has occurred in the cumulative value of the yAx increments. In this way, the gate circuit 139 operates to multiply the cumulative value of the yAx increments for an integrator by 5.

In FIGURE l, several bistable multivibrators such as the multivibrator 90 are shown. Furthermore, the construction and operation of these multivibrators have been disclosed above on a general basis. A specic circuit for use as such multivibrators is shown in FIGURE 8. The multivibrator includes a pair of tubes 184 and 185. The grid of each tube is connected to an appropriate output stage. For example, if the circuit shown in FIGURE 8 serves as the multivibrator 90` in FIGURE 1, the grid of the tube y184 would be connected to the output terminal of -the gate circuit 104' and the grid of the tube 185 would be connected to the out-put terminal of the or network 106. The cathodes of the tubes are connected to the coil 62 and to a suitable source of positive biasing voltages.

Connections are respectively made from the plates of the tubes 184 and 185 through suitable coupling capacitan-ces to the grids of tubes 186 and 187. The cathodes of the tubes 186 and 187 :are both connected through a suitable resistance and capacitance to a source of negative voltage. The plate of the tube 186 is coupled to the grid of the tube 187 by a suitable resistance 188 and capacitance 189 connected in parallel. Similarly, the plate of the tube 187 is coupled to the grid of the tube 186 through a res-istance 190 and a capacitance 191 connected in parallel.

The plate of the tube 186 is also connected 'to one terminal of a resistance 192, the other terminal of which is connected to an output line 193. Connections are made from the output line 193 to the cathode of a diode 194 and to the plate of a diode 195. The plate of the diode 194 is biased at approximately -25 v. and the cathode of the diode 195 is biased at approximately 0 v. The plate of the diode 194 and the cathode ot the diode 195 also have common terminals with the plate of a diode 196 and the cathode o'f a diode 197, respectively. The cathode of the dio-de 196 and the plate of the diode 197 are connected to an output line 198 and to one terminal of a resistance 199 having i-ts other te-rminal connected to Ithe plate of the tube 187.

Clock pulses are introduced to the cathodes of the tubes 184 and 185 from the coil `62 to reduce the voltages on these tubes from a positive voltage to approximately volt. Upon the simultaneous introduction of a positive pulse to the grid of one of the tubes, the tube conduct-s. For example, the tube 184 conducts when a positive pulse of voltage is introduced to it from the gate circuit 104. When the tube 184 conducts, the voltage on the plate oi the tube falls and causes the tube 186 to become cut off. Since `the tube 186 is no longer conductive, the voltage on the plate of this tube rises. This voltage is introduced through the resistance 188 and the capacitance 189 to the grid of the tube 187 to make the tube conductive.

Similarly the tube 187 becomes conductive when a pulse is introduced to the grid of the tube from the or network 106 at the same time that a clock pulse is introduced to the cathode of the tube from the coil 62. This causes the tube 187 to become cut off and a relatively high volt-age to be produced on the plate of the tube.

14 Upon the production of this high voltage, the tube 186 starts tol conduct. In this way, either the tube 186 or the tube 187 conducts at any one -time and the other tube is cut off.

The diodes 194, 195, 196 and 197 serve Ias a clamping network to maintain the voltages on the output lines 193 and 198 at either 0 volt or -25 volts. For example, when a potential of -25 volts is to be produced at the output line 193, current iiows through the diode 194 to maintain this potential -in case of any tendency of the voltage to become more negative than -25 volts. Similarly, the diode 195 passes -a current when a potent-iai of 0 volt is to be produced at the output line 193 and the potenti-al on the line tends to rise above 0 volt.

The system shown in FIGURE 1 and disclosed above is shown in some detail in FIGURES 2 through 7, inclusive. The system includes the channels 14, 16, 18, 20, 22, 24 and 26 and the coils respectively associated with the different channels. For example, the coils 27, 28 and 30 are associated with the channel 14. The coil 27 is connected to the grid of the lett tube in a bistable multivibrator 202 (FIGURE 2) and to the input terminal of an inverter 204, the output from which is introduced to the grid off the right tube in the multivibrator 202. In like manner, a multivibrator 206 and an inverter 208; a multivibrator 210 and an inverter 212; a multivibrator 214 and an inverter 216; a multivibrator 218 and an inverter 220; and a multivibrator 222 and an inverter 224 are respectively associated with the coils 32, 38, 44, 54 and 60.

vConnections are made from the plates of the left and right 4tubes in the multivibrator 206 to input terminals of gate circuits 228 and 230, respectively. Other input terminals o-f the gate circuits 228 and 230 are connected through a line 232 to a counter 234 corresponding to the counter 65 shown in FIGURE l. Similarly, the voltages on the plates of the left and right tubes in the multivibrator 210 are respectively introduced -to input terminals of gate lcircuits 236 and 238 having other input terminals connected through the line 232 to the counter 234.

The output signals from the gate circuits 228 and 230 respectively pass through or networks 240 and 242 to the grids of the left and right tubes in a bistable multivibrator 244. The voltage on the plate of the left tube in the multivibrator 244 is in lturn introduced through an or network 245 tothe coil 36 for recordation in the channel 16. In like manner, the signals from the gate circuits 236 and 238 respectively pass through or networks 246 and 248 to the grids of the left and right tubes in a bistable multivibrator 250. A connection is made from the plate of the left tube in the multivibrator 250 to the coil 42 for the recordation of information in the channel 18.

The voltage on the plate of the left tube in the multivibrator 206 is not only introduced to the gate circuit 228 but also to a gate circuit 254 having other input terminals connected to the line 232 and to the plate of the left Itube in the multivibrator 218. The output signals iro-m the gate circuit 254 pass -to input terminals of gate circuits 256 and 258, other input terminals of which are respectively connected to the plates of the left and right tubes in the multivibrator 222. The output terminals of the gate circuit 256 and 258' are connected to a Ay summing counter 260l corresponding to the counter shown in FIGURE l.

The output terminals Iof the Ay counter 260 are connected to input Aterminals of gate circuits such as circuits 262, 264, 266 and 268 having other input -terminals connected through a line 270 to the counter 234. Only certain of the gate circuits are showvn in FIGURE 2 for purposes of simplicity. The output terminals of the gate circuits such as the circuits 262, '264, 266 and 268 are in turn connected to the grids of the left and right tubes 

